View UPD753208GT_2590321.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1996 data sheet 4-bit single-chip microcontrollers the m pd753208 is one of the 75xl series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller. the m pd753208 has an on-chip lcd controller/driver and is based on the m pd75308b of the 75x series. however, the m pd75308b is supplied in an 80-pin package, whereas the m pd753208 is supplied in a 48- pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. in addition, the m pd753208 features expanded cpu functions and performs high-speed operations at a low voltage of 1.8 v. detailed information about functions can be found in the following users manual. be sure to read it before designing. m pd753208 users manual: u10158e document no. u10166ej2v0ds00 (2nd edition) date published march 1997 n printed in japan mos integrated circuit m pd753204, 753206, 753208 the information in this document is subject to change without notice. the mark shows major revised points. features ? low-voltage operation: v dd = 1.8 to 5.5 v C can be driven by two 1.5-v batteries ? internal memory C program memory (rom): 4096 8 bits ( m pd753204) 6144 8 bits ( m pd753206) 8192 8 bits ( m pd753208) C data memory (ram): 512 4 bits ? variable instruction execution time for high-speed operation and power saving operation C 0.95, 1.91, 3.81, 15.3 m s (@ 4.19-mhz operation) C 0.67, 1.33, 2.67, 10.7 m s (@ 6.0-mhz operation) ? internal programmable lcd controller/driver ? small package: 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) ? one-time prom version: m pd75p3216 applications remote controllers, cameras, sphygnomamometers, compact-disc radio cassette player compo systems, gas meters, etc. ordering information part number package rom ( 8 bits) m pd753204gt- 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) 4096 m pd753206gt- 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) 6144 m pd753208gt- 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) 8192 remark indicates rom code suffix. unless otherwise specified, references in this data sheet to the m pd753208 mean the m pd753204 and the m pd753206.
2 m pd753204, 753206, 753208 function outline parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19-mhz operation with system clock) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0-mhz operation with system clock) internal memory rom 4096 8 bits ( m pd753204) 6144 8 bits ( m pd753206) 8192 8 bits ( m pd753208) ram 512 4 bits general-purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/ cmos input 6 connecting on-chip pull-up resistors can be specified by software: 5 output cmos input/output 20 connecting on-chip pull-up resistors can be specified by software: 20 port also used for segment pins: 8 n-ch open-drain 4 on-chip pull-up resistors can be specified by mask option input/output 13-v withstand voltage total 30 lcd controller/driver ? segment selection: 4/8/12 segments (can be changed to cmos input/ output port in 4-time units; max. 8) ? display mode selection: static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) ? on-chip split resistor for lcd drive can be specified by mask option timer 5 channels ? 8-bit timer/event counter: 1 channel ? 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier generator, and timer with gate) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode ... msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) ? f , 524, 262, 65.5 khz (@ 4.19-mhz operation with system clock) ? f , 750, 375, 93.8 khz (@ 6.0-mhz operation with system clock) buzzer output (buz) ? 2, 4, 32 khz (@ 4.19-mhz operation with system clock) ? 2.93, 5.86, 46.9 khz (@ 6.0-mhz with system clock) vectored interrupts external: 2, internal: 5 test input external: 1, internal: 1 system clock oscillator ceramic or crystal oscillator for system clock oscillation standby function stop/halt mode power supply voltage v dd = 1.8 to 5.5 v package 48-pin plastic shrink sop (375 mils, 0.65-mm pitch)
3 m pd753204, 753206, 753208 contents 1. pin configuration (top view) .................................................................................................... 5 2. block diagram ................................................................................................................................ 6 3. pin functions .................................................................................................................................... 7 3.1 port pins ......................................................................................................................................7 3.2 non-port pins .............................................................................................................................. 9 3.3 pin input/output circuits ......................................................................................................... 11 3.4 recommended connections for unused pins ....................................................................... 13 4. switching function between mk i mode and mk ii mode ................................................ 14 4.1 difference between mk i and mk ii modes .............................................................................. 14 4.2 setting method of stack bank select register (sbs) ........................................................... 15 5. memory configuration ............................................................................................................. 16 6. peripheral hardware function ........................................................................................... 21 6.1 digital i/o port ........................................................................................................................... 21 6.2 clock generator ........................................................................................................................ 22 6.3 clock output circuit ................................................................................................................. 23 6.4 basic interval timer/watchdog timer ..................................................................................... 24 6.5 watch timer .............................................................................................................................. 25 6.6 timer/event counter ................................................................................................................. 26 6.7 serial interface .......................................................................................................................... 30 6.8 lcd controller/driver ............................................................................................................... 32 6.9 bit sequential buffer ................................................................................................................ 34 7. interrupt function and test function .............................................................................. 35 8. standby function ........................................................................................................................ 37 9. reset function ............................................................................................................................. 38 10. mask option ................................................................................................................................... 41 11. instruction set ............................................................................................................................ 42 12. electrical specifications ....................................................................................................... 56 13. characteristic curves (reference values) ................................................................... 68 14. package drawings ..................................................................................................................... 70 15. recommended soldering conditions ................................................................................. 71
4 m pd753204, 753206, 753208 appendix a m pd753108, 753208, and 75p3216 functional list ............................................. 72 appendix b development tools ................................................................................................. 74 appendix c related documents ................................................................................................ 77
5 m pd753204, 753206, 753208 1. pin configuration (top view) ? 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) m pd753204gt - , m pd753206gt- , m pd753208gt- note connect ic (internally connected) pin directly to v dd . pin identification p00 to p03 : port0 s12 to s23 : segment output 12 to 23 p10, p13 : port1 v lc0 to v lc2 : lcd power supply 0 to 2 p20 to p23 : port2 bias : lcd power supply bias control p30 to p33 : port3 lcdcl : lcd clock p50 to p53 : port5 sync : lcd synchronization p60 to p63 : port6 ti0 : timer input 0 p80 to p83 : port8 pto0 to pto2 : programmable timer output 0 to 2 p90 to p93 : port9 buz : buzzer clock kr0 to kr3 : key return 0 to 3 pcl : programmable clock com0 to com3 : common output 0 to 3 int0, int4 : external vectored interrupt 0, 4 sck : serial clock x1, x2 : system clock oscillation 1, 2 si : serial input reset : reset so : serial output ic : internally connected sb0, sb1 : serial data bus 0, 1 v dd : positive power supply v ss : ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p30/lcdcl p31/sync p32 p33 v ss p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 v dd x1 x2 s12 s13 s14 s15 p93/s16 p92/s17 p91/s18 p90/s19 p83/s20 p82/s21 p81/s22 p80/s23 p23/buz p22/pcl/pto2 p21/pto1 p20/pto0 p13/ti0 p10/int0 p03/si/sb1 p02/so/sb0 p01/sck p00/int4 reset ic note
6 m pd753204, 753206, 753208 2. block diagram note the rom capacity depends on the product. port0 port1 port2 port3 port5 port6 port8 port9 4 2 4 4 4 4 4 4 p00 to p03 p10,p13 p20 to p23 p30 to p33 p50 to p53 p60 to p63 p80 to p83 p90 to p93 s12 to s15 4 4 4 4 s16/p93 to s19/p90 s20/p83 to s23/p80 com0 to com3 v lc0 v lc1 v lc2 bias lcdcl/p30 sync/p31 f lcd lcd controller/ driver int0/p10 4 intw cpu clock f ic v dd v ss reset standby control system clock generator x1 x2 clock divider clock output control pcl/pto2/p22 f x /2 n interrupt control bit seq buffer (16) intcsi tout intt2 clocked serial interface 8-bit timer counter #1 8-bit timer counter #2 cascaded 16-bit timer counter pto1/p21 tout pto2/pcl/p22 sp (8) sbs bank general reg. data memory (ram) 512 4 bits cy alu program counter program memory note (rom) f lcd watch timer basic interval timer/ watchdog timer buz/p23 ti0/p13 tpo0/p20 8-bit timer/event counter #0 intt1 intt0 tout si/sb1/p03 so/sb0/p02 sck/p01 int4/p00 kr0/p60 to kr3/p63 decode and control intbt
7 m pd753204, 753206, 753208 3. pin function 3.1 port pins (1/2) pin name input/output alternate function 8-bit after reset i/o circuit function i/o type note 1 p00 input int4 no input (b) p01 input/output sck (f)-a p02 input/output so/sb0 (f)-b p03 input/output si/sb1 (m)-c p10 input int0 no input (b)-c p13 ti0 p20 input/output pto0 no input e-b p21 pto1 p22 pcl/pto2 p23 buz p30 input/output lcdcl no input e-b p31 sync p32 C p33 C p50 to input/output C no m-d p53 note 2 notes 1. characters in parentheses indicate the schmitt-trigger input. 2. if on-chip pull-up resistors are not specified by mask option (when used as n-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 4-bit input port (port0). for p01 to p03, on-chip pull-up resistors can be specified by software in 3-bit units. high level (when pull- up resistors are provided) or high- impedance input port in 1 bit unit (port1). on-chip pull-up resistors can be specified by software in 2-bit units. noise elimination circuit can be specified with p10/int0. 4-bit input/output port (port2). on-chip pull-up resistors can be specified by software in 4-bit units. programmable 4-bit input/output port (port3). this port can be specified input/output bit- wise. on-chip pull-up resistor can be speci- fied by software in 4-bit units. n-ch open-drain 4-bit input/output port (port5). a pull-up resistor can be contained bit-wise (mask option). withstand voltage is 13 v in open-drain mode.
8 m pd753204, 753206, 753208 3.1 port pins (2/2) pin name input/output alternate function 8-bit after reset i/o circuit function i/o type note 1 p60 input/output kr0 no input (f)-a p61 kr1 p62 kr2 p63 kr3 p80 input/output s23 yes input h p81 s22 p82 s21 p83 s20 p90 input/output s19 input h p91 s18 p92 s17 p93 s16 notes 1. characters in parentheses indicate the schmitt-trigger input. 2. do not connect on-chip pull-up resistors specified by software when using as segment signal output pins. programmable 4-bit input/output port (port6). this port can be specified for input/output bit- wise. on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (port8). on-chip pull-up resistors can be specified by software in 4-bit units. note 2 4-bit input/output port (port9). on-chip pull-up resistors can be specified by software in 4-bit units. note 2
9 m pd753204, 753206, 753208 3.2 non-port pins (1/2) pin name input/output alternate function after reset i/o circuit function type note 1 ti0 input p13 inputs external event pulses to the timer/event input (b)-c counter. pto0 output p20 timer/event counter output input e-b pto1 p21 timer counter output pto2 p22/pcl pcl p22/pto2 clock output buz p23 optional frequency output (for buzzer output or system clock trimming) sck input/output p01 serial clock input/output input (f)-a so/sb0 p02 serial data output (f)-b serial data bus input/output si/sb1 p03 serial data input (m)-c serial data bus input/output int4 input p00 edge detection vectored interrupt input (both input (b) rising edge and falling edge detection) int0 input p10 input (b)-c kr0 to kr3 input/output p60 to p63 falling edge detection testable input input (f)-a s12 to s15 output C segment signal output note 2 g-a s16 to s19 output p93 to p90 segment signal output input h s20 to s23 output p83 to p80 segment signal output input h com0 to com3 output C common signal output note 2 g-b v lc0 to v lc2 C C lcd drive power C C on-chip split resistor is enable (mask option). bias output C output for external split resistor disconnect note 3 C lcdcl note 4 input/output p30 clock output for externally expanded driver input e-b sync note 4 input/output p31 clock output for externally expanded driver sync input e-b notes 1. characters in parentheses indicate the schmitt trigger input. 2. each display output selects the following vlcx as input source. s12 to s15: v lc1 , com0 to com2: v lc2 , com3: v lc0 . 3. when a split resistor is contained ....... low level when no split resistor is contained ......high-impedance 4. these pins are provided for future system expansion. at present, these pins are used only as pins p30 and p31. edge detection vectored with clock elimination interrupt input (detection circuit/asynchronous edge can be selected). selectable noise elimination circuit can be specified.
10 m pd753204, 753206, 753208 3.2 non-port pins (2/2) pin name input/output alternate function after reset i/o circuit function type note 1 x1 input C crystal/ceramic connection pin for the system C C clock oscillator. when inputting the external clock, input the external clock to pin x1, and x2 C the reverse phase of the external clock to pin x2. reset input C system reset input (low-level active) C (b) ic C C internally connected. connect directly to v dd .C C v dd C C positive power supply C C v ss C C ground potential C C note characters in parentheses indicate the schmitt-trigger input.
11 m pd753204, 753206, 753208 3.3 pin input/output circuits the m pd753208 pin input/output circuits are shown schematically. type a type b type d type e-b type b-c type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. enable p.u.r. p-ch in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt trigger input having hysteresis characteristic. cmos specification input buffer. push-pull output that can be placed in output high-impedance (both p-ch, n-ch off). p.u.r. v dd (1/2)
12 m pd753204, 753206, 753208 type f-b type h type g-a type m-d type m-c v dd p.u.r enable p.u.r p-ch p-ch v dd n-ch output disable (p) data output disable output disable (n) in/out p.u.r : pull-up resistor data output disable p.u.r. enable p.u.r v dd p-ch in/out n-ch p.u.r : pull-up resistor v lc1 p-ch n-ch out n-ch v lc2 n-ch com data p-ch in/out n-ch (+13-v withstand) v dd data output disable p.u.r. (mask option) p.u.r. : pull-up resistor voltage control circuit pull-up resistor that only operates upon the execution of an input instruction when the pull-up resistor is not connected via the mask option (it is available during low-voltage). note v dd p-ch p.u.r. note input instruction type g-b v lc0 v lc1 seg data v lc2 n-ch seg data data output disable type g-a type e-b in/out (2/2) p-ch n-ch v lc0 p-ch n-ch p-ch n-ch p-ch n-ch out n-ch p-ch n-ch p-ch n-ch p-ch n-ch
13 m pd753204, 753206, 753208 3.4 recommended connections for unused pins table 3-1. list of recommended connections for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect individually to v ss or v dd via a resistor p02/so/sb0 p03/si/sb1 connect to v ss p10/int0 connect to v ss or v dd p13/ti0 p20/pto0 input state: connect individually to v ss or v dd via a resistor p21/pto1 output state: no connection p22/pcl/pto2 p23/buz p30/lcdcl p31/sync p32 p33 p50 to p53 input state : connect to v ss output state : connect to v ss (do not connect pull-up resistor in the mask option) p60/kr0 to p63/kr3 input state : connect individually to v ss or v dd via a resistor output state : no connection s0 to s15 no connection com0 to com3 s16/p93 to s19/p90 input state: connect individually to v ss or v dd via a resistor s20/p83 to s23/p80 output state: no connection v lc0 to v lc2 connect to v ss bias only if all of v lc0 to v lc2 are unused, connect to v ss . in other cases, no connection. ic connect to v dd directly
14 m pd753204, 753206, 753208 4 switching function between mk i mode and mk ii mode 4.1 difference between mk i and mk ii modes the cpu of the m pd753208 has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by bit 3 of the stack bank select register (sbs). ? mk i mode: upward compatible with the m pd75308b. can be used in the 75xl cpu with a rom capacity of up to 16 kbytes. ? mk ii mode: incompatible with m pd75308b. can be used in all the 75xl cpu including those products whose rom capacity is more than 16 kbytes. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode number of stack bytes 2 bytes 3 bytes for subroutine instructions bra ! addr1 instruction not available available calla ! addr1 instruction call ! addr instruction 3 machine cycles 4 machine cycles callf ! faddr instruction 2 machine cycles 3 machine cycles caution the mkii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. software compatibility with products whose program memory exceeds 16 kbytes can be raised by using this mode. when the mkii mode is selected, the number of stack bytes increases by one byte per stack during subroutine call instruction execution compared with the mki mode. when the !faddr instruction is used, the length of each machine cycle increases by 1 machine cycle. therefore, if ram efficiency or processing speed is emphasized over software compatibility, use of the mki mode is recommended.
15 m pd753204, 753206, 753208 caution since sbs. 3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs. 3 to 0 to select the mk ii mode. 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the sbs. figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 100 b note at the beginning of a program. when using the mk ii mode, it must be initialized to 000 b note . note the desired numbers must be set in the positions. figure 4-1. stack bank select register format sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 01 0 1 0 memory bank 0 memory bank 1 other than above 0 must be set in the bit 2 position. stack area specification mk ii mode mk i mode mode switching specification setting prohibited
16 m pd753204, 753206, 753208 5. memory configuration program memory (rom) .... 4096 8 bits ( m pd753204) .... 6144 8 bits ( m pd753206) .... 8192 8 bits ( m pd753208) C addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset and start are possible at an arbitrary address. C addresses 0002h to 000dh vector table wherein the program start address and values set for the rbe and mbe by the vectored interrupts are written. interrupt execution can be started at an arbitrary address. C addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. it is used to decrease the program steps. ? data memory (ram) C data area ... 512 words 4 bits (000h to 1ffh) C peripheral hardware area ... 128 words 4 bits (f80h to fffh)
17 m pd753204, 753206, 753208 figure 5-1. program memory map (1/3) (a) m pd753204 note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction. 000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 004h mbe rbe 0 0 int0 (high-order 4 bits) start address 006h 008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 00ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 00ch mbe rbe 0 0 intt1/intt2 (high-order 4 bits) start address 020h 07fh 080h 7ffh 800h fffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) brcb ! caddr instruction branch address call !addr instruction subroutine entry address br $addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address intcsi start address intt0 start address intt1/intt2 start address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instructions callf ! faddr instruction entry address
18 m pd753204, 753206, 753208 figure 5-1. program memory map (2/3) (b) m pd753206 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 17ffh geti instruction reference table 000ch mbe rbe 0 intt1/intt2 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address brcb ! caddr instruction branch address branch address of br bcxa, br bcde, br ! addr, bra ! addr1 note or calla ! addr1 note instructions call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb ! caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 intcsi intt0 intt1/intt2 start address start address start address start address start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction.
19 m pd753204, 753206, 753208 figure 5-1. program memory map (3/3) (c) m pd753208 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 1fffh geti instruction reference table 000ch mbe rbe 0 intt1/intt2 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address brcb ! caddr instruction branch address branch address of br bcxa, br bcde, br ! addr, bra ! addr1 note or calla ! addr1 note instructions call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb ! caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 intcsi intt0 intt1/intt2 start address start address start address start address start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction.
20 m pd753204, 753206, 753208 figure 5-2. data memory map note as a stack area, either memory bank 0 or 1 can be selected. data area static ram (512 4) stack area note general-purpose register area 000h 01fh 0ffh 100h 1ebh 1ech 1f7h 1f8h 1ffh f80h fffh display data memory area peripheral hardware area data memory memory bank 0 (32 4) 256 4 (224 4) 256 4 (236 4) (12 4) (8 4) not incorporated 128 4 15 1 020h
21 m pd753204, 753206, 753208 6. peripheral hardware function 6.1 digital i/o port there are three kinds of i/o ports. ? cmos input ports (ports 0, 1) : 6 ? cmos input/output ports (ports 2, 3, 6, 8, 9) : 20 ? n-ch open-drain input/output ports (port 5) : 4 total 30 table 6-1. types and features of digital ports port function operation and features remarks port0 4-bit input the alternate function pins have an output function also used for the int4, sck, with operation mode when using the serial interface so/sb0, and si/sb1 pins. function. port1 1-bit input 2-bit input dedicated port also used for the int0 and ti0. port2 4-bit i/o can be set to input mode or output mode in 4-bit also used for the pto0 to units. pto2, pcl, and buz pins. port3 can be set to input mode or output mode bit-wise. also used for the lcdcl and sync pins. port5 4-bit i/o (n- can be set to input mode or output mode in 4-bit channel open- units. on-chip pull-up resistor can be specified drain, 13-v by mask option bit-wise. withstand) port6 4-bit i/o can be set to input mode or output mode bit-wise. also used for the kr0 to kr3 pins. port8 can be set to input mode ports 8 and 9 are paired also used for the s20 to or output mode in 4-bit and data can be input/ s23 pins. units. output in 8-bit units. port9 also used for the s16 to s19 pins.
22 m pd753204, 753206, 753208 6.2 clock generator the clock generator provides the clock signals to the cpu and peripheral hardware and its configuration is shown in figure 6-1. the operation of the clock generator is determined by the processor clock control register (pcc). the instruction execution time can also be changed. ? 0.95, 1.91, 3.81, 15.3 m s (system clock: @ 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (system clock: @ 6.0-mhz operation) figure 6-1. clock generator block diagram note instruction execution 4 f ? ? ? y ? ? ? t y t v dd x2 x1 f x oscillation stop system clock oscillator 1/2 1/4 1/16 1/1 to 1/4096 divider selector divider 1/4 ?cpu ?int0 noise eliminator ?clock output circuit halt f/f s rq wait release signal from bt reset signal standby release signal from interrupt control circuit s r q f/f stop pcc2, pcc3 clear stop note pcc2 pcc3 pcc1 pcc0 pcc halt note internal bus ?basic interval timer (bt) ?timer/event counter 0 ?timer counter 1, 2 ?watch timer ?lcd controller/driver ?serial interface ?int0 noise eliminator ?clock output circuit
23 m pd753204, 753206, 753208 from clock generator f f x /2 3 f x /2 4 f x /2 6 selector clom3 0 clom1 clom0 4 clom p22 output latch port 2 i/o mode specification bit port2.2 bit 2 of pmgb internal bus output buffer pcl/pto2/p22 from timer counter (channel 2) selector remarks 1. f x = system clock frequency 2. f = cpu clock 3. pcc: processor clock control register 4. one clock cycle (t cy ) of the cpu clock is equal to one machine cycle of the instruction. 6.3 clock output circuit the clock output circuit is provided to output the clock pulses from the pcl pin (also functions as p22 or pto2) to the remote control wave outputs and peripheral lsis. ? clock output (pcl) : f , 524, 262, 65.5 khz (system clock: @ 4.19-mhz operation) f , 750, 375, 93.8 khz (system clock: @ 6.0-mhz operation) figure 6-2. clock output circuit block diagram remark special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
24 m pd753204, 753206, 753208 from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 81 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released. set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt 6.4 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. ? interval timer operation to generate a reference time interrupt ? watchdog timer operation to detect program runaway and reset the cpu ? selects and counts the wait time when the standby mode is released ? reads the contents of counting figure 6-3. basic interval timer/watchdog timer block diagram note instruction execution
25 m pd753204, 753206, 753208 6.5 watch timer the m pd753208 has one watch timer channel, whose functions are as follows. ? sets the test flag (irqw) with 0.5 sec interval. the standby mode can be released by the irqw. ? 0.5 sec interval can be created with the system clock (4.194304 mhz) ? convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. ? outputs a frequency (2.048, 4.096, or 32.768 khz) to the buz pin (p23), usable for buzzer and trimming of system clock frequencies. ? clears the frequency divider to make the clock start with zero seconds. figure 6-4. watch timer block diagram from clock generator selector f x 128 (32.768 khz) f w (32.768 khz) divider 4 khz 2 khz f w 2 3 f w 2 4 clear selector f w 2 7 f w 2 6 (512 hz : 1.95 ms) (256 hz : 3.91 ms) f w 2 14 selector 2 hz 0.5 sec irqw set signal intw f lcd output buffer pmgb bit 2 port2.3 wm wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output-latch port 2 input/ output mode 8 internal bus p23/buz note 2 note 1 notes 1. wm3 is undefined while reading data. 2. be sure to set wm0 to 0. remark the values enclosed in parentheses are applied when f x = 4.194304 mhz.
26 m pd753204, 753206, 753208 6.6 timer/event counter the m pd753208 provides one channel for timer/event counters and two channels for timer counters. figures 6-5 to 6-7 show the block diagrams. timer/event counter functions are as follows. ? programmable interval timer operation ? square wave output of any frequency to the pto0 pin (n = 0 to 2). ? event counter operation (channel 0 only) ? divides the frequency of signal input via the ti0 pin to 1-nth of the original signal and outputs the divided frequency to the pto0 pin (frequency divider operation). ? supplies the shift clock to the serial interface circuit. ? reads the counting status. the timer/event counter operates in the following four modes as set by the mode register. table 6-2. operation modes of timer/event counter channel channel 0 channel 1 channel 2 mode 8-bit timer/event counter mode note 1 aa a gate control function n/a note 2 n/a a pwm pulse generator mode n/a n/a a 16-bit timer counter mode n/a a gate control function n/a note 2 a carrier generator mode n/a a notes 1. channel 0 only. 8-bit timer counter mode for channel 1 and channel 2 2. used for gate control signal generation remark a: available n/a: not available
27 m pd753204, 753206, 753208 figure 6-5. timer/event counter block diagram (channel 0) note execution of instruction caution when data is set to tm0, always set bit 1 to 0. port1.3 input buffer ti0/p13 f x /2 4 f x /2 6 f x /2 8 f x /2 10 from clock generator mpx tm06 tm05 tm04 tm03 tm02 888 8 8 tm0 set1 note modulo register (8) comparator (8) count register (8) tmod0 t0 cp timer operation start clear match tout f/f reset t0 enable flag p20 output latch port 2 input/output mode toe0 port2.0 pmgb bit 2 to serial interface pto0/p20 intt0 irqt0 set signal reset irqt0 clear signal to timer counter (channel 2) internal bus output buffer tout0
28 m pd753204, 753206, 753208 figure 6-6. timer/event counter block diagram (channel 1) note execution of instruction from clock generator mpx tm16 tm15 tm14 tm13 tm12 tm11 tm10 tm1 decoder 16 bit timer counter mode cp timer operation start selector clear 8 8 8 8 modulo register (8) comparator (8) count register (8) timer counter match signal (channel 2) (during 16-bit timer counter mode) timer counter comparator (channel 2) (during 16-bit timer counter mode) timer counter reload signal (channel 2) t1 tmod1 match tout f/f reset t1 enable flag p21 output latch port 2 input/output mode intt1 irqt1 set signal irqt1 clear signal reset toe1 port2.1 pmgb bit 2 p21/pto1 output buffer internal bus timer counter (channel 2) output f x /2 5 f x /2 6 f x /2 8 f x /2 10 f x /2 12 set1 note
29 m pd753204, 753206, 753208 figure 6-7. timer counter block diagram (channel 2) note execution of instruction tm25 tm26 tm24 tm23 tm22 tm21 tm20 tm2 8 8 tc2 decoder high-level period setting modulo register (8) modulo register (8) tgce toe2 remc nrzb nrz reload mpx (8) comparator (8) count register (8) 8 8 clear 16-bit timer counter mode timer operation start timer counter match signal (channel 1) (during 16-bit timer counter mode) timer counter clear signal (channel 1) (during 16-bit timer counter mode) timer counter match signal (channel 1) (when carrier generator mode) match overflow carrier generator mode port2.2 pmgb bit 2 p22 output latch output buffer p22/pcl/pto2 timer clock input (channel 1) intt2 irqt2 set signal irqt2 clear signal reset t2 tmod2 tmod2h internal bus cp timer event counter tout f/f (channel 0) reset 8 8 8 selector selector port 2 input/output tout f/f 8 from clock generator mpx selector from clock generator f x /2 4 f x /2 2 f x /2 f x /2 6 f x /2 8 f x /2 10 set1 note
30 m pd753204, 753206, 753208 6.7 serial interface the m pd753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode (serial bus interface mode)
31 m pd753204, 753206, 753208 figure 6-8. serial interface block diagram internal bus 8 8 8 8/4 bit manipulation bit test sbic slave address register (sva) address comparator shift register (sio) (8) (8) (8) relt cmdt so latch set clr dq csim p03/si/sb1 p02/so/sb0 p01/sck p01 output iatch bus release/ command/ acknowledge detection circuit reld cmdd ackd ackt serial clock counter serial clock control circuit serial clock selector intcsi control circuit acke bsye busy/ acknowledge output circuit intcsi irqcsi set signal f x /2 3 f x /2 4 f x /2 6 tout0 (from timer/event counter (channel 0)) bit test match signal selector selector external sck
32 m pd753204, 753206, 753208 6.8 lcd controller/driver the m pd753208 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the panel directly. the m pd753208 lcd controller/driver functions are as follows: ? display data memory is read automatically by dma operation and segment and common signals are generated. ? display mode can be selected from among the following five: <1> static <2> 1/2 duty (time multiplexing by 2), 1/2 bias <3> 1/3 duty (time multiplexing by 3), 1/2 bias <4> 1/3 duty (time multiplexing by 3), 1/3 bias <5> 1/4 duty (time multiplexing by 4), 1/3 bias ? a frame frequency can be selected from among four in each display mode. ? a maximum of 12 segment signal output pins (s12 to s23) and four common signal output pins (com0 to com3). ? the segment signal output pins (s16 to s23) can be changed to the i/o ports (port8 and port9). ? split-resistor can be incorporated to supply lcd drive power. (mask option) C various bias methods and lcd drive voltages can be applicable. C when display is off, current flowing through the split resistor is cut. ? display data memory not used for display can be used for normal data memory.
33 m pd753204, 753206, 753208 figure 6-9. lcd controller/driver block diagram port 8 output latch 3 2 1 0 port 9 output latch 3 2 1 0 port mode register group c 0 1 lcd/port selection register 1f7h 3210 1f0h 3210 1efh 3210 1ech 3210 display mode register display control register port 3 output latch 10 port mode register group a 10 4 4 4 8 4 8 4 4 4 4 internal bus 4 port 8 input/output buffer 01 2 3 port 9 input/output buffer 01 2 3 s23/p80 s16/p93 s15 s0 com3 com2 com1 com0 v lc2 v lc1 v lc0 p31/sync p30/lcdcl lcd drive mode switching lcd drive voltage control common driver segment driver segment driver 3210 3210 3210 3210 timing controller f lcd decoder
34 m pd753204, 753206, 753208 address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h 6.9 bit sequential buffer ....... 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. figure 6-10. bit sequential buffer format remarks 1. in pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in pmem.@l addressing, the bsb can be manipulated regardless of mbe/msb specification.
35 m pd753204, 753206, 753208 7. interrupt function and test function there are seven interrupt sources and two test sources in the m pd753208. the interrupt control circuit of the m pd753208 has the following functions. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (ie ) and interrupt master enable flag (ime). ? can set any interrupt start address. ? multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irq ). an interrupt generated can be checked by software. ? release the standby mode. a release interrupt can be selected by the interrupt enable flag. (2) test function ? test request flag (irq ) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag.
36 m pd753204, 753206, 753208 internal bus interruput enable flag (ie ) irqbt irq4 irq0 irqcsi irqt0 irqt1 irqt2 irqw irq2 intcsi intt0 intt1 intt2 intw both edge detector edge detector selec- tor int4/p00 int0/p10 kr0/p60 kr3/p63 falling edge detector selec- tor im2 standby release signal priority control circuit vector table address generator decoder ime ips ist0 vrqn note im2 im0 24 intbt ist1 figure 7-1. interrupt control circuit block diagram note noise eliminator (standby release is disabled when noise eliminator is selected.)
37 m pd753204, 753206, 753208 8. standby function in order to save power dissipation while a program is in standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd753208. table 8-1. operation status in standby mode item mode stop mode halt mode set instruction stop instruction halt instruction operation clock generator the system clock stops oscillation. only the cpu clock f halts (oscillation status continues). basic interval timer/ operation stops. operable only when the system clock watchdog timer is oscillated. (the irqbt is set in the reference interval). serial interface operable only when an external sck operable input is selected as the serial clock. timer/event counter operable only when a signal input to operable the ti0 pin is specified as the count clock. watch timer operation stops. operable lcd controller/driver operation stops. operable external interrupt the int4 is operable. only the int0 is not operated note . cpu operation stops. release signal interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or reset signal input. note can operate only when the noise eliminator is not used (im02 = 1) by bit 2 of the edge detection mode register (im0).
38 m pd753204, 753206, 753208 reset internal reset signal reset signal sent from the basic interval timer/watchdog timer wdtm internal bus operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation 9. reset function there are two reset inputs: external reset signal and reset signal sent from the basic interval timer/ watchdog timer. when either one of the reset signals are input, an internal reset signal is generated. figure 9-1 shows the circuit diagram of the above two inputs. figure 9-1. configuration of reset function each hardware is initialized by the reset signal generation as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation note the following two times can be selected by the mask option. 2 17 /f x (21.8 ms: @ 6.0-mhz operation, 31.3 ms: @ 4.19-mhz operation) 2 15 /f x (5.46 ms: @ 6.0-mhz operation, 7.81 ms: @ 4.19-mhz operation)
39 m pd753204, 753206, 753208 table 9-1. status of each device after reset (1/2) hardware reset signal generation reset signal generation in the standby mode during operation program counter (pc) m pd753204 sets the low-order 4 bits of sets the low-order 4 bits of program memorys address program memorys address 0000h to pc11 to pc8 and 0000h to pc11 to pc8 and the contents of address 0001h the contents of address 0001h to pc7 to pc0. to pc7 to pc0. m pd753206, sets the low-order 5 bits of sets the low-order 5 bits of m pd753208 program memory's address program memory's address 0000h to pc12 to pc8 and 0000h to pc12 to pc8 and the contents of address 0001h the contents of address 0001h to pc7 to pc0. to pc7 to pc0. psw carry flag (cy) held undefined skip flag (sk0-sk2) 0 0 interrupt status flag (ist0, ist1) 0 0 bank enable flag (mbe, rbe) sets bit 6 of program memorys sets bit 6 of program memorys address 0000h to rbe and bit address 0000h to rbe and bit 7 to mbe. 7 to mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/watchdog mode register (btm) 0 0 timer watchdog timer enable flag (wdtm) 00 timer/event counter (t0) 0 0 counter (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer counter (t1) 0 0 counter (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 timer counter (t2) 0 0 counter (t2) modulo register (tmod2) ffh ffh high-level period setting modulo ffh ffh register (tmod2h) mode register (tm2) 0 0 toe2, tout f/f 0, 0 0, 0 remc, nrz, nrzb 0, 0, 0 0, 0, 0 tgce 0 0 watch timer mode register (wm) 0 0
40 m pd753204, 753206, 753208 table 9-1. status of each device after reset (2/2) hardware reset signal generation reset signal generation in the standby mode during operation serial interface shift register (sio) held undefined operation mode register (csim) 0 0 sbi control register (sbic) 0 0 slave address register (sva) held undefined clock generator, processor clock control register (pcc) 0 0 clock output circuit clock output mode register (clom) 0 0 lcd controller/ display mode register (lcdm) 0 0 driver display control register (lcdc) 0 0 lcd/port selection register (lps) 0 0 interrupt interrupt request flag (irq ) reset (0) reset (0) function interrupt enable flag (ie )0 0 interrupt priority selection register (ips) 00 int0, 2 mode registers (im0, im2) 0, 0 0, 0 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, b, c) 0 0 pull-up resistor setting register (poga, b) 00 bit sequential buffer (bsb0 to bsb3) held undefined
41 m pd753204, 753206, 753208 10. mask option the m pd753208 has the following mask options. ? p50 to p53 mask options selects whether or not to connect an internal pull-up resistor. <1> connect pull-up resistor internally bit-wise. <2> do not connect pull-up resistor internally. ?v lc0 to v lc2 pins, bias pins mask option selects whether or not to internally connect lcd-driving split resistors. <1> do not connect split resistor internally. <2> connect four 10-k w (typ.) split resistors simultaneously internally. <3> connect four 100-k w (typ.) split resistors simultaneously internally. ? standby function mask option selects the wait time with the reset signal. <1> 2 17 /fx (21.8 ms: when f x = 6.0 mhz, 31.3 ms: when f x = 4.19 mhz) <2> 2 15 /fx (5.46 ms: when f x = 6.0 mhz, 7.81 ms: when f x = 4.19 mhz)
42 m pd753204, 753206, 753208 11. instruction set (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to "ra75x assembler package users manuallanguage (eeu-1363)" . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers and labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, see the user's manual. representation description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 000h-fffh immediate data or label ( m pd753204) 0000h-17ffh immediate data or label ( m pd753206) 0000h-1fffh immediate data or label ( m pd753208) addr1 000h-fffh immediate data or label ( m pd753204) (only in the 0000h-17ffh immediate data or label ( m pd753206) mkii mode) 0000h-1fffh immediate data or label ( m pd753208) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (where bit 0 = 0) or label portn port0-port3, port5, port6, port8, port9 ie iebt, iet0-iet2, ie0, ie2, ie4, iecsi, iew rbn rb0-rb3 mbn mb0, mb1, mb15 note mem can be only used for even address in 8-bit data processing.
43 m pd753204, 753206, 753208 (2) legend in explanation of operation a : a register, 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : xa register pair; 8-bit accumulator bc : bc register pair de : de register pair hl : hl register pair xa : xa expanded register pair bc : bc expanded register pair de : de expanded register pair hl : hl expanded register pair pc : program counter sp : stack pointer cy : carry flag, bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 3, 5, 6, 8, 9) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : separation between address and bit ( ) : contents addressed by h : hexadecimal data
44 m pd753204, 753206, 753208 (3) explanation of symbols under addressing area column *1 mb = mbe?mbs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h-07fh) mb = 15 (f80h-fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 m pd753204 addr = 000h-fffh m pd753206 addr = 0000h-17ffh m pd753208 addr = 0000h-1fffh *7 addr, addr1 = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 *8 m pd753204 caddr = 000h-fffh m pd753206 caddr = 0000h-0fffh(pc 12 = 0) or program memory addressing 1000h-17ffh(pc 12 = 1) m pd753208 caddr = 0000h-0fffh(pc 12 = 0) or 1000h-1fffh(pc 12 = 1) *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 m pd753204 addr1 = 000h-fffh m pd753206 addr1 = 0000h-17ffh m pd753208 addr1 = 0000h-1fffh remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock (= t cy ); time can be selected from among four types by setting pcc.
45 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a ? n4 string effect a instruction reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string effect a hl, #n8 2 2 hl ? n8 string effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2+s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2+s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp'
46 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area table movt xa, @pcde 1 3 l m pd753204 reference xa ? (pc 11C8 +de) rom l m pd753206, 753208 xa ? (pc 12C8 +de) rom xa, @pcxa 1 3 l m pd753204 xa ? (pc 11C8 +xa) rom l m pd753206, 753208 xa ? (pc 12C8 +xa) rom xa, @bcde 1 3 xa ? (bcde) rom note *6 xa, @bcxa 1 3 xa ? (bcxa) rom note *6 bit transfer mov1 cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) ? cy *1 operation adds a, #n4 1 1+s a ? a+n4 carry xa, #n8 2 2+s xa ? xa+n8 carry a, @hl 1 1+s a ? a+(hl) *1 carry xa, rp' 2 2+s xa ? xa+rp' carry rp'1, xa 2 2+s rp'1 ? rp'1+xa carry addc a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp' 2 2 xa, cy ? xa+rp'+cy rp'1, xa 2 2 rp'1, cy ? rp'1+xa+cy subs a, @hl 1 1+s a ? aC(hl) *1 borrow xa, rp' 2 2+s xa ? xaCrp' borrow rp'1, xa 2 2+s rp'1 ? rp'1Cxa borrow subc a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp' 2 2 xa, cy ? xaCrp'Ccy rp'1, xa 2 2 rp'1, cy ? rp'1CxaCcy note set "0" to register b if the m pd753204 is used. only the low-order one bit of register b will be valid if the m pd753206 or 753208 is used.
47 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area operation and a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa or a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa xor a, #n4 2 2 a ? a v n4 a, @hl 1 1 a ? a v (hl) *1 xa, rp' 2 2 xa ? xa v rp' rp'1, xa 2 2 rp'1 ? rp'1 v xa accumulator rorc a 1 1 cy ? a 0 , a 3 ? cy, a nC1 ? a n manipulation instructions not a 2 2 a ? a increment incs reg 1 1+s reg ? reg+1 reg=0 and decrement rp1 1 1+s rp1 ? rp1+1 rp1=00h instructions @hl 2 2+s (hl) ? (hl)+1 *1 (hl)=0 mem 2 2+s (mem) ? (mem)+1 *3 (mem)=0 decs reg 1 1+s reg ? regC1 reg=fh rp' 2 2+s rp' ? rp'C1 rp'=ffh comparison ske reg, #n4 2 2+s skip if reg = n4 reg=n4 instruction @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a=reg xa, rp' 2 2+s skip if xa = rp' xa=rp' carry flag set1 cy 1 1 cy ? 1 manipulation instruction clr1 cy 1 1 cy ? 0 skt cy 1 1+s skip if cy = 1 cy=1 not1 cy 1 1 cy ? cy
48 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area memory bit set1 mem.bit 2 2 (mem.bit) ? 1 *3 manipulation instructions fmem.bit 2 2 (fmem.bit) ? 1 *4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 1 *5 @h+mem.bit 2 2 (h+mem 3C0 .bit) ? 1 *1 clr1 mem.bit 2 2 (mem.bit) ? 0 *3 fmem.bit 2 2 (fmem.bit) ? 0 *4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 0 *5 @h+mem.bit 2 2 (h+mem 3C0 .bit) ? 0 *1 skt mem.bit 2 2+s skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy ? cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy v (h+mem 3C0 .bit) *1
49 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br note addr C C ? m pd753204 *6 instructions pc 11C0 ? addr select the most appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. ? m pd753206, 753208 pc 12C0 ? addr select the most appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. addr1 C C ? m pd753204 *11 pc 11-0 ? addr1 select the most appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. ? m pd753206, 753208 pc 12C0 ? addr1 select the most appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. ! addr 3 3 ? m pd753204 *6 pc 11C0 ? addr ? m pd753206, 753208 pc 12C0 ? addr $addr 1 2 ? m pd753204 *7 pc 11C0 ? addr ? m pd753206, 753208 pc 12C0 ? addr $addr1 1 2 ? m pd753204 pc 11C0 ? addr1 ? m pd753206, 753208 pc 12C0 ? addr1 note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
50 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br pcde 2 3 ? m pd753204 instruction pc 11C0 ? pc 11-8 +de ? m pd753206, 753208 pc 12C0 ? pc 12-8 +de pcxa 2 3 ? m pd753204 pc 11C0 ? pc 11-8 +xa ? m pd753206, 753208 pc 12C0 ? pc 12-8 +xa bcde 2 3 ? m pd753204 *6 pc 11C0 ? bcde note 1 ? m pd753206, 753208 pc 12C0 ? bcde note 2 bcxa 2 3 ? m pd753204 *6 pc 11C0 ? bcxa note 1 ? m pd753206, 753208 pc 12C0 ? bcxa note 2 bra note 3 !addr1 3 3 ? m pd753204 *6 pc 11C0 ? addr1 ? m pd753206, 753208 pc 12C0 ? addr1 brcb !caddr 2 2 ? m pd753204 *8 pc 11C0 ? caddr 11C0 ? m pd753206, 753208 pc 12C0 ? pc 12 +caddr 11C0 subroutine calla note 3 !addr1 3 3 ? m pd753204 *11 stack control (spC2) ? , , mbe, rbe instructions (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, 0 pc 11C0 ? addr1, sp ? spC6 ? m pd753206, 753208 (spC2) ? , , mbe, rbe (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, pc 12 pc 12C0 ? addr1, sp ? spC6 notes 1. "0" must be set to the b register. 2. only the low-order one bit is valid in the b register. 3. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
51 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine call note !addr 3 3 ? m pd753204 *6 stack control (spC3) ? mbe, rbe, 0, 0 instructions (spC4) (spC1) (spC2) ? pc 11C0 pc 11C0 ? addr, sp ? spC4 ? m pd753206, 753208 (spC3) ? mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) ? pc 11C0 pc 12C0 ? addr, sp ? spC4 4 ? m pd753204 (spC2) ? , , mbe, rbe (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, 0 pc 11C0 ? addr, sp ? spC6 ? m pd753206, 753208 (spC2) ? , , mbe, rbe (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, pc 12 pc 12C0 ? addr, sp ? spC6 callf note !faddr 2 2 ? m pd753204 *9 (spC3) ? mbe, rbe, 0, 0 (spC4) (spC1) (spC2) ? pc 11C0 pc 11C0 ? 0+faddr, sp ? spC4 ? m pd753206, 753208 (spC3) ? mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) ? pc 11C0 pc 12C0 ? 00+faddr, sp ? spC4 3 ? m pd753204 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, 0 pc 11C0 ? 0+faddr, sp ? spC6 ? m pd753206, 753208 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, pc 12 pc 12C0 ? 00+faddr, sp ? spC6 note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. ? ?
52 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine ret note 13 ? m pd753204 stack control pc 11C0 ? (sp) (sp+3) (sp+2) instructions mbe, rbe, 0, 0 ? (sp+1), sp ? sp+4 ? m pd753206, 753208 pc 11C0 ? (sp) (sp+3) (sp+2) mbe, rbe, 0, pc 12 ? (sp+1), sp ? sp+4 ? m pd753204 , , mbe, rbe ? (sp+4) 0, 0, 0, 0, ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2), sp ? sp+6 ? m pd753206, 753208 , , mbe, rbe ? (sp+4) mbe, 0, 0, pc 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2), sp ? sp+6 rets note 1 3+s ? m pd753204 unconditional mbe, rbe, 0, 0 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 then skip unconditionally ? m pd753206, 753208 mbe, rbe, 0, pc 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 then skip unconditionally ? m pd753204 0, 0, 0, 0 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) , , mbe, rbe ? (sp+4) sp ? sp+6 then skip unconditionally ? m pd753206, 753208 0, 0, 0, pc 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) , , mbe, rbe ? (sp+4) sp ? sp+4 then skip unconditionally note the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
53 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine reti note 1 13 ? m pd753204 stack control mbe, rbe, 0, 0 ? (sp+1) instructions pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 ? m pd753206, 753208 mbe, rbe, 0, pc 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 ? m pd753204 0, 0, 0, 0 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 ? m pd753206, 753208 0, 0, 0, pc 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 push rp 1 1 (spC1)(spC2) ? rp, sp ? spC2 bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 pop rp 1 1 rp ? (sp+1) (sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 interrupt ei 2 2 ime (ips.3) ? 1 control instructions ie 22ie ? 1 di 2 2 ime (ips.3) ? 0 ie 22ie ? 0 input/output in note 2 a, portn 2 2 a ? portn (n = 0-3, 5, 6, 8, 9) instructions xa, portn 2 2 xa ? portn+1, portn (n = 8) out note 2 portn, a 2 2 portn ? a (n = 3, 5, 6, 8, 9) portn, xa 2 2 portn+1, portn ? xa (n = 8) cpu control halt 2 2 set halt mode (pcc.2 ? 1) instructions stop 2 2 set stop mode (pcc.3 ? 1) nop 1 1 no operation special sel rbn 2 2 rbs ? n (n = 0-3) instructions mbn 2 2 mbs ? n (n = 0, 1, 15) notes 1. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. while the in instruction and out instruction are being executed, the mbe must be set to 0 or 1 and mbs must be set to 15.
54 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area special get notes 1, 2 taddr 1 3 ? m pd753204 *10 instructions ? when tbr instruction pc 11C0 ? (taddr) 3C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) ? pc 11C0 (spC3) ? mbe, rbe, 0, 0 pc 11C0 ? (taddr) 3C0 + (taddr+1) sp ? spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction ? m pd753206, 753208 ? when tbr instruction pc 12C0 ? (taddr) 4C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) ? pc 11C0 (spC3) ? mbe, rbe, 0, pc 12 pc 12C0 ? (taddr) 4C0 + (taddr+1) sp ? spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 ? m pd753204 *10 ? when tbr instruction pc 11C0 ? (taddr) 3C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, 0 (spC2) ? , , mbe, rbe pc 11C0 ? (taddr) 3C0 + (taddr+1) sp ? spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. 2. the above operations in the double boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC - CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC -
55 m pd753204, 753206, 753208 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area special geti notes 1, 2 taddr 1 3 ? m pd753206, 753208 *10 instructions ? when tbr instruction pc 12C0 ? (taddr) 4C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) ? pc 11C0 (spC5) ? 0, 0, 0, pc 12 (spC2) ? , , mbe, rbe pc 12C0 ? (taddr) 4C0 + (taddr+1) sp ? spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. 2. the above operations in the double boxes can be performed only in the mk ii mode. CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC
56 m pd753204, 753206, 753208 12. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v input voltage v i1 except port 5 C0.3 to v dd + 0.3 v v i2 port 5 on-chip pull-up resistor C0.3 to v dd + 0.3 v when n-ch open-drain C0.3 to +14 v output voltage v o C0.3 to v dd + 0.3 v output current high i oh per pin C10 ma total for all pins C30 ma output current low i ol per pin 30 ma total for all pins 220 ma operating ambient t a C40 to +85 note ?c temperature storage temperature t stg C65 to +150 ?c note when lcd is driven in normal mode: t a = C10 to +85?c caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25?c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf
57 m pd753204, 753206, 753208 system clock oscillator characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit ceramic oscillator 1.0 6.0 note 2 mhz resonator frequency (f x ) note 1 oscillation after v dd reaches oscil- 4 ms stabilization time note 3 lation voltage range min. crystal oscillator 1.0 6.0 note 2 mhz resonator frequency (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input 1.0 6.0 note 2 mhz clock frequency (f x ) note 1 x1 input 83.3 500 ns high/low level width (t xh , t xl ) notes 1. the oscillator frequency and x1 input frequency indicate characteristics of the oscillator only. for the instruction execution time, refer to the ac characteristics. 2. when the oscillator frequency is 4.19 mhz < fx 6.0 mhz, setting the processor clock control register (pcc) to 0011 results in 1 machine cycle being less than the required 0.95 m s. therefore, set pcc to a value other than 0011. 3. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd or releasing the stop mode. caution when using the system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v dd . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. x2 x1 c1 c2 v dd x2 x1 c1 c2 v dd x1 x2
58 m pd753204, 753206, 753208 recommended oscillator constants ceramic resonator (ta = e40 to 85 c) manufacturer part number frequency oscillator constant (pf) oscillation voltage range (v dd ) remark (mhz) c1 c2 min. (v) max. (v) tdk ccr1000k2 1.0 100 100 1.8 5.5 ccr2.0mc33 2.0 2.0 on-chip ccr3.58mc3 3.58 capacitor ccr4.19mc3 4.19 fcr4.19mc5 2.2 ccr6.0mc3 6.0 fcr6.0mc5 2.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillaiton frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
59 m pd753204, 753206, 753208 dc characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output voltage low i ol per pin 15 ma sum of the all pins 150 ma input voltage high v ih1 ports 2, 3, 8, and 9 2.7 v dd 5.5 v 0.7v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0.8v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih3 port 5 when a pull-up register 2.7 v dd 5.5 v 0.7v dd v dd v is incorporated 1.8 v dd < 2.7 v 0.9v dd v dd v when n-ch open-drain 2.7 v dd 5.5 v 0.7v dd 13 v 1.8 v dd < 2.7 v 0.9v dd 13 v v ih4 x1 v dd C 0.1 v dd v input voltage low vi l1 ports 2, 3, 5, 8, and 9 2.7 v dd 5.5 v 0 0.3v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0 0.2v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il3 x1 0 0.1 v output voltage high v oh sck, so, ports 2, 3, 6, 8, and 9 i oh = C1.0 ma v dd C 0.5 v output voltage low v ol1 sck, so, ports 2, 3, 5, 6, 8, i ol = 15 ma, 0.2 2.0 v and 9 v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open-drain 0.2v dd v pull-up resistor 3 1 k w input leakage i lih1 v in = v dd other pins than x1 3 m a current high i lih2 x1 20 m a i lih3 v in = 13 v port 5 (when n-ch open-drain) 20 m a input leakage i lil1 v in = 0 v other pins than port 5 and x1 C3 m a current low i lil2 x1 C20 m a i lil3 port 5 (when n-ch open drain) C3 m a other than when an input instruction is executed port 5 (when n-ch open-drain) C30 m a when an input instruction v dd = 5.0 v C10 C27 m a is executed v dd = 3.0 v C3 C8 m a output leakage i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 8 3 m a current high and 9 port 5 (when a pull-up resistor is incorporated.) i loh2 v out = 13 v port 5 (when n-ch open-drain) 20 m a output leakage i lol v out = 0 v C3 m a current low on-chip pull-up resistor r l1 v in = 0 v ports 0 to 3, 6, 8, and 9 50 100 200 k w (excluding p00 pin) r l2 port 5 (mask option) 15 30 60 k w
60 m pd753204, 753206, 753208 dc characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 t a = C40 to +85?c 2.7 v dd v t a = C10 to +85?c 2.2 v dd v vac0 = 1 1.8 v dd v vac current note 1 i vac vac0 = 1, v dd = 2.0 v 10% 1 4 m a lcd split resistor note 2 r lcd1 50 100 200 k w r lcd2 51020k w lcd output voltage v odc l o = 1.0 m av lcd0 = v lcd 0 0.2 v deviation note 3 (common) v lcd1 = v lcd 2/3 lcd output voltage v ods l o = 0.5 m a v lcd2 = v lcd 1/3 0 0.2 v deviation note 3 (segment) 1.8 v v lcd v dd supply current note 4 i dd1 6.0 mhz v dd = 5.0 v 10% note 5 1.9 6.0 ma crystal oscillation v dd = 3.0 v 10% note 6 0.4 1.3 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.72 2.1 ma v dd = 3.0 v 10% 0.27 0.8 ma i dd1 4.19 mhz v dd = 5.0 v 10% note 5 1.5 4.0 ma crystal oscillation v dd = 3.0 v 10% note 6 0.25 0.75 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.7 2.0 ma v dd = 3.0 v 10% 0.23 0.7 ma i dd3 stop mode v dd = 5.0 v 10% 0.05 10 m a v dd = 3.0 v 0.02 5 m a 10% t a = 25?c 0.02 3 m a notes 1. set vac0 to 0 when setting the stop mode. if vac0 is set to 1, the current increases by about 1 m a. 2. either r lcd1 or r lcd2 can be selected by the mask option. 3. the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). 4. not including currents flowing in on-chip pull-up resistors or lcd split resistors. 5. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high- speed mode. 6. when pcc is set to 0000 and the device is operated in the low-speed mode.
61 m pd753204, 753206, 753208 ac characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle t cy v dd = 2.7 to 5.5 v 0.67 64 m s time note 1 0.95 64 m s ti0 input frequency f ti v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz ti0 input t tih , t til v dd = 2.7 to 5.5 v 0.48 m s high/low-level width 1.8 m s interrupt input high/ t inth , int0 im02 = 0 note 2 m s low-level width t intl im02 = 1 10 m s int4 10 m s kr0 to kr3 10 m s reset low level width t rsl 10 m s notes 1. the cycle time (minimum instruc- tion execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the con- nected resonator (and external clock) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic. 2. 2t cy or 128/f x is set by setting the interrupt mode register (im0). 1 0 23456 0.5 1 3 4 5 6 30 64 supply voltage v dd [v] t cy vs v dd cycle time t cy [ s] guaranteed operation range m
62 m pd753204, 753206, 753208 serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output): (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high/low-level t kl1 , t kh1 v dd = 2.7 to 5.5 v t kcy1 /2 C 50 ns width t kcy1 /2 C 150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns so note 1 output delay t kso1 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 250 ns time from sck c l = 100 pf 0 1000 ns notes 1. in the 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines. 2-wire and 3-wire serial i/o mode (sck...external clock input): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high/low-level t kl2 , t kh2 v dd = 2.7 to 5.5 v 400 ns width 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns so note 1 output delay t kso2 r l = 1 k w , note 2 v dd = 2.7 to 5.5 v 0 300 ns time from sck c l = 100 pf 0 1000 ns notes 1. in the 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines.
63 m pd753204, 753206, 753208 sbi mode (sck...internal clock output (master)): (t a = e40 to +85 ?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high/low-level t kl3 , t kh3 v dd = 2.7 to 5.5 v t kcy3 /2 C 50 ns width t kcy3 /2 C 150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns sb0, 1 hold time t ksi3 v dd = 2.7 to 5.5 v t kcy3 /2 ns (from sck - ) sb0, 1 output delay t kso3 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 250 ns time from sck c l = 100 pf 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 - t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l are the load resistance and load capacitance of the sb0 and sb1 output lines. sbi mode (sck...external clock input (slave)): (t a = C40 to +85 ?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high/low-level t kl4 , t kh4 v dd = 2.7 to 5.5 v 400 ns width 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns sb0, 1 hold time t ksi4 v dd = 2.7 to 5.5 v t kcy4 /2 ns (from sck - ) sb0, 1 output delay t kso4 r l = 1 k w , note v dd = 2.7 to 5.5 v 0 300 ns time from sck c l = 100 pf 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 - t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l are the load resistance and load capacitance of the sb0 and sb1 output lines.
64 m pd753204, 753206, 753208 x1 input 1/f x t xl t xh 0.1 v v dd ?.1 v ti0 1/f ti t til t tih ac timing test point (excluding x1 input) v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) clock timing ti0 timing
65 m pd753204, 753206, 753208 t kcy1, 2 t kl1, 2 t kh1, 2 sck si so t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t kso1, 2 t sik1, 2 t kl1, 2 t kh1, 2 sck t ksi1, 2 sb0, 1 t kcy1, 2 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode
66 m pd753204, 753206, 753208 t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t sbh t sbl t ksb t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t ksb t rsl reset t intl t inth intp0, 4 kr0 to 3 serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing
67 m pd753204, 753206, 753208 data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85?c) parameter symbol test conditions min. typ. max. unit release signal set time t srel 0 m s oscillation stabilization t wait release by reset note 2 ms wait time note 1 release by interrupt note 3 ms notes 1. the oscillation stabillization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 2. either 2 17 /f x or 2 15 /f x can be selected by the mask option. 3. depends on the basic interval timer mode register (btm) settings (see the table below). btm3 btm2 btm1 btm0 wait time when fx = 4.19-mhz operation when fx = 6.0-mhz operation 0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) 0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) 1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) 1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode t srel t wait t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request)
68 m pd753204, 753206, 753208 01234567 8 0.01 0.05 0.1 0.5 1.0 5.0 10 supply current i dd (ma) (t a = 25 c) i dd vs v dd (system clock : 6.0-mhz crystal resonator) supply voltage v dd (v) pcc = 0000 system clock halt mode pcc = 0001 pcc = 0010 v dd 22 pf crystal resonator 6.0 mhz 22 pf x1 x2 pcc = 0011 13. characteristic curves (reference values)
69 m pd753204, 753206, 753208 01234567 8 0.01 0.05 0.1 0.5 1.0 5.0 10 supply current i dd (ma) (t a = 25 c) i dd vs v dd (system clock : 4.19-mhz crystal resonator) supply voltage v dd (v) pcc = 0011 pcc = 0000 system clock halt mode pcc = 0001 pcc = 0010 v dd 22 pf crystal resonator 4.19 mhz 22 pf x1 x2
70 m pd753204, 753206, 753208 48 pin plastic shrink sop (375 mil) c b d e f g a 124 48 25 l i h j k detail of lead end 3 m m n +7 ? p48gt-65-375b-1 item millimeters inches a b c d e f g h i j k 16.21 max. 0.65 (t.p.) 2.0 max. 1.7 0.1 10.0 0.3 0.63 max. 0.639 max. 0.005 0.003 0.079 max. 0.394 0.315 0.008 0.025 max. note l m 0.5 0.2 0.15 1.0 0.2 8.0 0.2 0.004 0.020 +0.008 ?.009 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.067 0.004 0.026 (t.p.) 0.006 n 0.10 0.004 0.012 0.30 0.10 0.125 0.075 +0.004 ?.002 0.10 +0.10 ?.05 +0.004 ?.005 +0.012 ?.013 0.039 +0.009 ?.008 14. package drawings
71 m pd753204, 753206, 753208 15. recommended soldering conditions the m pd753208 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 15-1. surface mounting type soldering conditions m pd753204gt-xxx : 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) m pd753206gt-xxx : 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) m pd753208gt-xxx : 48-pin plastic shrink sop (375 mils, 0.65-mm pitch) soldering soldering conditions symbol method infrared rays peak package's surface temperature: 235?c, reflow time: 30 seconds or less ir35-00-2 reflow (at 210?c or higher), number of reflow processes: twice max. vps peak package's surface temperature: 215?c, reflow time: 40 seconds or less vp15-00-2 (at 200?c or higher), number of reflow processes: twice max. wave soldering solder temperature: 260?c or below, flow time: 10 seconds or less, number of ws60-00-1 flow process: 1, preheating temperature: 120?c or below (package surface temperature) partial heating pin temperature: 300?c or below, time: 3 seconds or less (per device side) caution use of more than one soldering method should be avoided (except for partial heating).
72 m pd753204, 753206, 753208 appendix a m pd753108, 753208, and 75p3216 functional list parameter m pd753108 m pd753208 m pd75p3216 program memory mask rom one-time prom 0000h-1fffh 0000h-3fffh (8192 8 bits) (16384 8 bits) data memory 000h-1ffh (512 4 bits) cpu 75xl cpu instruction when main system ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19-mhz operation) execution clock is selected ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0-mhz operation) time when subsystem 122 m s (@ 32.768-khz none clock is selected operation) i/o port cmos input 8 (on-chip pull-up resistors can 6 (on-chip pull-up resistors can be specified by software: 5) be specified by software: 7) cmos input/output 20 (on-chip pull-up resistors can be specified by software) n-ch open drain 4 (on-chip pull-up resistors can be specified by software, 4 (no mask option, withstand input/output withstand voltage is 13 v) voltage is 13 v) total 32 30 lcd controller/driver segment selection: 16/20/24 segment selection: 4/8/12 segments (can be changed to cmos (can be changed to cmos input/output port in 4 time-unit; input/output port in 4 time- max. 8) unit; max. 8) display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) on-chip split resistor for lcd driver can be specified by no on-chip split resistor for using mask option. lcd driver timer 5 channels 5 channels ? 8-bit timer/event ? 8-bit timer counter: 2 channels (can be used as the 16-bit counter: 3 channels timer counter, carrier generator, and timer with gate) ? basic interval timer/ ? 8-bit timer/event counter: 1 channel watchdog timer: 1 channel ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel ? watch timer: 1 channel clock output (pcl) ? f , 524, 262, 65.5 khz (main system clock: @ 4.19-mhz operation) ? f , 750, 375, 93.8 khz (main system clock: @ 6.0-mhz operation) buzzer output (buz) ? 2, 4, 32 khz ? 2, 4, 32 khz (main system clock: @ (main system clock: @ 4.19-mhz operation) 4.19-mhz operation or sub- ? 2.93, 5.86, 46.9 khz system clock: @ 32.768-khz (main system clock: @ 6.0-mhz operation) operation) ? 2.86, 5.72, 45.8 khz (main system clock: @ 6.0-mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode ... msb/lsb can be selected for transfer top bit ? 2-wire serial i/o mode ? sbi mode scc register contained none sos register vectored interrupt external: 3, internal: 5 external: 2, internal: 5
73 m pd753204, 753206, 753208 parameter m pd753108 m pd753208 m pd75p3216 test input external: 1, internal: 1 operation supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 64-pin plastic qfp ? 48-pin plastic shrink sop (14 14 mm) (375 mils, 0.65-mm pitch) ? 64-pin plastic qfp (12 12 mm)
74 m pd753204, 753206, 753208 appendix b development tools the following development tools are provided for system development using the m pd753208. in 75xl series, the relocatable assembler which is common to the m pd753208 subseries is used in combination with the device file of each product. language processor ra75x relocatable assembler host machine part number os distribution media (product name) pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra75x ver. 3.30 to 5-inch 2hd m s5a10ra75x ver. 6.2 note ibm pc/at tm and refer to section 3.5-inch 2hc m s7b13ra75x compatible machines os for ibm pc 5-inch 2hc m s7b10ra75x device file host machine part number os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13df753208 ver. 3.30 to 5-inch 2hd m s5a10df753208 ver. 6.2 note ibm pc/at and refer to section 3.5-inch 2hc m s7b13df753208 compatible machines os for ibm pc 5-inch 2hc m s7b10df753208 prom write tools hardware pg-1500 pg-1500 is a prom programmer which enables you to program single chip microcomputers including prom by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to pg-1500. it also enables you to program typical prom devices of 256 kbits to 4 mbits. pa-75p3216gt prom programmer adapter for the m pd75p3216gt. connect the programmer adapter to pg-1500 for use. software pg-1500 controller pg-1500 and a host machine are connected by serial and parallel interfaces and pg-1500 is controlled on the host machine. host machine part number os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver. 3.30 to 5-inch 2hd m s5a10pg1500 ver. 6.2 note ibm pc/at and refer to section 3.5-inch 2hd m s7b13pg1500 compatible machines os for ibm pc 5-inch 2hc m s7b10pg1500 note ver. 5.00 or later have the task swap function, but it cannot be used for this software. remarks 1. operation of the assembler and device file is guaranteed only on the above host machine and oss. 2. operation of the pg-1500 controller is guaranteed only on the above host machine and oss.
75 m pd753204, 753206, 753208 debugging tool the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd753208. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753208 subseries, the emulation board ie-75300-r-em and emulation probe ep- 753208gt-r that are sold separately must be used with the ie-75000-r. by connecting with the host machine and the prom programmer, efficient debugging can be made. it contains the emulation board ie-75000-r-em which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd753208 subseries, the emulation board ie-75300-r-em and emulation probe ep- 753208gt-r which are sold separately must be used with the ie-75001-r. it can debug the system efficiently by connecting the host machine and prom programmer. ie-75300-r-em emulation board for evaluating the application systems that use a m pd753208 subseries. it must be used with the ie-75000-r or ie-75001-r. ep-753208gt-r emulation probe for the m pd753208gt. it must be connected to the ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 48-pin conversion adapter ev-9500gf-48 which facilitates ev-9500gf-48 connection to a target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronix i/f and controls the above hardware on a host machine. host machine part no. os distribution media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver. 3.30 to 5-inch 2hd m s5a10ie75x ver. 6.2 note 2 ibm pc/at and its refer to section 3.5-inch 2hc m s7b13ie75x compatible machine os for ibm pc 5-inch 2hc m s7b10ie75x notes 1. maintenance parts. 2. ver. 5.00 or later have the task swap function, but it cannot be used for this software. remarks 1. operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m pd753204, 753206, 753208, and 75p3216 are commonly referred to as the m pd753208 subseries.
76 m pd753204, 753206, 753208 os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note english version is supported. caution ver. 5.0 and later have the task swap function, but it cannot be used for this software.
77 m pd753204, 753206, 753208 appendix c related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document no. document name japanese english m pd753204, 753206, 753208 data sheet u10166j this manual m pd75p3216 data sheet u10241j u10241e m pd753208 users manual u10158j u10158e 75xl series selection guide u10453j u10453e documents related to development tool document no. document name japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j u11354e ep-753208gt-r users manual u10739j u10739e pg-1500 users manual u11940j eeu-1335 software ra75x assembler package users manual operation eeu-731 eeu-1346 language eeu-730 eeu-1363 pg-1500 controller users manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document no. document name japanese english semiconductor device package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 iei-1201 guide to quality assurance for semiconductor devices c11893j mei-1202 microcontroller C related product guide C third party products C c11416j C caution the contents of the documents listed above are subject to change without prior notice to users. make sure to use the latest edition when starting design.
78 m pd753204, 753206, 753208 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
79 m pd753204, 753206, 753208 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
80 m pd753204, 753206, 753208 ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

▲Up To Search▲

Price & Availability of UPD753208GT

	To Download UPD753208GT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .